It is highly desirable to scale down erase voltages of a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory device, which has typically been achieved by decreasing the thickness of the tunneling oxide layer. However, conventional SONOS memory device has a conductive storage layer, and thus thin tunneling oxide layers will cause a significant leakage problem. Stored charges are more likely to be leaked to the substrate through a thin tunneling oxide layer than through a thick one.